View XR16M752IL32-F_6255331.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

xr16m752 -high performance duart with 64-byte fifo home news careers investor relations contact us partnernet login search communications interface power management support info request how to order samples how to buy design technical documentation technical faqs product finder product tree technical support packaging evaluation boards cross references product change notifications obsolescence interface brochure ibis models bsdl ici uart finder xr16m752 print this page high performance duart with 64-byte fifo features l 1.62 to 3.6 volt operation l pin-to-pin and software compatible to ti's tl16c752b and philips' sc16c752b in the 48-tqfp package m two independent uart channels m data rate of up to 16 mbps at 3.3 v m data rate of up to 12.5 mbps at 2.5 v m data rate of up to 8 mbps at 1.8 v m fractional baud rate generator m data sampling rates of 16x, 8x and 4x m transmit and receive fifos of 64 bytes m programmable tx and rx fifo trigger levels m automatic hardware (rts/cts) flow control m automatic software (xon/xoff) flow control m halt and resume transmission control m automatic rs-485 half-duplex direction control output via rts# m wireless infrared (irda 1.0) encoder/decoder m automatic sleep mode m full modem interface l crystal oscillator (up to 24mhz) or external clock (up to 64mhz) input l 48-tqfp and 32-qfn packages l pb-free, rohs compliant versions offered applications l portable appliances l telecommunication network routers l ethernet network routers l cellular data devices l factory automation and process controls description the xr16m752 1 (m752) is a high performance dual universal asynchronous receiver and transmitter (uart) with 64 byte tx and rx fifos. the m752 operates from 1.62 to 3.63 volts. it is pin-to-pin and software compatible to the tl16c752b and sc16c752b, but with additional features such as a programmable fractional baud rate generator, automatic rs-485 half-duplex direction control, infrared mode specifications ch 2 cpuinterface intel data rate@5/3.3/2.5v na/16/12.5 tx/rxfifo(bytes) 64/64 tx/rxfifoctrs no tx/rxfifoint trig 4 levels/ 4 levels autorts/cts yes irdasup yes 5vtolinputs no sup v 1.62-3.63 pkgs tqfp-48, qfn-32 documents datasheets datasheet version 1.1.1 june 2009 1.18 mb application notes dan-190, exar uarts in rs- 485 applications version 1.0.0 april 2008 147.31 kb schematics isa eval board schematic version 2.1.0 august 2007 144.11 kb http://www.exar.com/common/content/productdetails.aspx?id=xr16m752 (1 of 2) [31-jul-09 2:52:52 pm]
xr16m752 -high performance duart with 64-byte fifo quality and reliability quality & reliability homepage material declaration sheets quality manual quarterly quality & reliability report rohs-green solutions related news 7/31/2006 - exar introduces high performance (16mbps), low voltage (1.8v) dual uart product family and 8x and 4x sampling rate. the standard features include 16 selectable tx and rx fifo trigger levels, automatic hardware (rts/cts) and software (xon/xoff) flow control, and a complete modem interface. onboard registers provide the user with operational status and data error flags. an internal loopback capability allows system diagnostics. each channel is independently programmable for data rates up to 16 mbps at 3.3 volt with a 4x sampling rate. the m752 is available in the 48-pin tqfp and 32-pin qfn packages. note: 1 covered by u.s. patent #5,649,122 for uart technical support or to obtain an ibis model for this product, please email exar's uart technical support group. part number pkg code rohs min temp. (c) max temp. (c) status buy now order samples XR16M752IL32-F qfn32 -40 85 active xr16m752im48-f tqfp48 -40 85 active part status legend active - the part is released for sale, standard product. eol (end of life) - the part is no longer being manufactured, there may or may not be inventory still in stock. cf (contact factory) - the part is still active but customers should check with the factory for availability. longer lead-times may apply. pre (pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. obs (obsolete) - the part is no longer being manufactured and may not be ordered. nrnd (not recommended for new designs) - the part is not recommended for new designs. ? 2000-2009 exar corporation, fremont california, u.s.a. terms of use | site map http://www.exar.com/common/content/productdetails.aspx?id=xr16m752 (2 of 2) [31-jul-09 2:52:52 pm]
exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr16m752/xr68m752 high performance duart with 64-byte fifo june 2009 rev. 1.1.1 general description the xr16m752/xr68m752 1 (m752) is a high performance dual universal asynchronous receiver and transmitter (uart) with 64 byte tx and rx fifos. the m752 operates from 1.62 to 3.63 volts. it is pin-to-pin and softwa re compatible to the tl16c752b and sc16c752b, but with additional features such as a programmable fractional baud rate generator, automatic rs-485 half-duplex direction control, infrared mode and 8x and 4x sampling rate. the standard features include 16 selectable tx and rx fifo trigger levels, automatic hardware (rts/ cts) and software (xon/xoff) flow control, and a complete modem interface. onboard registers provide the user with operational status and data error flags. an internal loopback capability allows system diagnostics. each channel is independently programmable for data rates up to 16 mbps at 3.3v with a 4x sampling rate. the xr68m752 has an additional 16/68# pin to select between the intel and motorola bus interface. the m752 is available in the 48-pin tqfp, 32-pin qfn and 49-pin stbga packages. n ote : 1 covered by u.s. patent #5,649,122 applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls features ? 1.62 to 3.6 volt operation ? pin-to-pin and software compatible to ti?s tl16c752b and philips? sc16c752b in the 48- tqfp package ? two independent uart channels data rate of up to 16 mbps at 3.3 v data rate of up to 12.5 mbps at 2.5 v data rate of up to 8 mbps at 1.8 v fractional baud rate generator data sampling rates of 16x, 8x and 4x transmit and receive fifos of 64 bytes programmable tx and rx fifo trigger levels automatic hardware (rts/cts) flow control automatic software (xon/xoff) flow control halt and resume transmission control automatic rs-485 ha lf-duplex direction control output via rts# wireless infrared (irda 1.0) encoder/decoder automatic sleep mode full modem interface ? crystal oscillator (up to 24mhz) or external clock (up to 64mhz) input ? 48-tqfp, 32-qfn and 49-stbga packages f igure 1. xr16m752 b lock d iagram xtal1 xtal2 crystal osc/buffer txa, rxa, dtra#, dsra#, rtsa#, dtsa#, cda#, ria#, op2a# 8-bit data bus interface uart channel a 64 byte tx fifo brg ir endec tx & rx uart regs 1.62 to 3.63 volt vcc gnd txb, rxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib#, op2b# uart channel b (same as channel a) a2:a0 d7:d0 csa# (cs#) csb# (a3) inta (irq#) intb (nc) iow# (r/w#) ior# (nc) reset/reset# txrdya# txrdyb# rxrdya# rxrdyb# 64 byte rx fifo 16/68#
f igure 2. p in o ut a ssignment - tqfp and qfn p ackages 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# nc xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# nc reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 nc d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# nc xr16m752 48-pin tqfp intel mode only 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb csa# csb# xtal1 xtal2 iow# gnd ior# rtsb# ctsb# reset rtsa# inta intb a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# xr16m752 32-pin qfn intel mode only 28 27 26 25 18 17 nc nc 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb csa# csb# xtal1 xtal2 iow# gnd ior# rtsb# ctsb# reset rtsa# inta intb a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# xr68m752 32-pin qfn intel mode 28 27 26 25 18 17 nc 16/68# vcc 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb cs# a3 xtal1 xtal2 r/w# gnd nc rtsb# ctsb# reset# rtsa# irq# nc a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# xr68m752 32-pin qfn motorola mode 28 27 26 25 18 17 nc 16/68# gnd 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# nc xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# nc xr68m752 48- pin tqfp intel mode nc vcc 16 # /68 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# cs# a3 nc xtal1 xtal2 r/w# cdb# gnd rxrdyb# nc dsrb# rib# rtsb# ctsb# reset# dtrb# dtra# rtsa# op2a# rxrdya# irq# nc a0 a1 a2 d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# nc xr68m752 48- pin tqfp motorola mode nc gnd 16 # /68 xr16m752/xr68m752 2 high performance duart with 64-byte fifo rev. 1.1.1
f igure 3. p in o ut a ssignment - stbga p ackage 1 2 3 4 5 6 7 a b c d e f g transparent top view a1 corner nc d3 d0 ria# ctsa# rs485# dtra# d5 d4 d1 d2 vcc dsra# reset d6 d7 rxb txrdya# cda# op2a# dtrb# txb rxa txa txrdyb# rtsa# inta intb csb# csa# op2b# rib# rxrdya# a0 a1 pwrsave iow# cdb# rxrdyb# dsrb# ctsb# enir# xtal1 xtal2 gnd ior# rtsb# 16/68# a2 ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16m752il32 32-pin qfn -40c to +85c active xr16m752im48 48-lead tqfp -40c to +85c active xr68m752il32 32-pin qfn -40c to +85c active xr68m752im48 48-lead tqfp -40c to +85c active xr68m752ib49 49-pin stbga -40c to +85c active xr16m752/xr68m752 3 rev. 1.1.1 high performance duart with 64-byte fifo
xr16m752/xr68m752 4 high performance duart with 64-byte fifo rev. 1.1.1 pin descriptions pin description n ame 32-qfn p in # 48-tqfp p in # 49-stbga p in # t ype d escription data bus interface a2 a1 a0 18 19 20 26 27 28 g7 e7 e6 i address data lines [2:0]. these 3 address lines select one of the internal register s in uart channel a/b during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 2 1 32 31 30 29 28 27 3 2 1 48 47 46 45 44 c2 c1 b1 b2 a2 b4 b3 a3 i/o data bus lines [7:0] (bidirectional). ior# (nc) 14 19 g4 i when 16/68# pin is high, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge inst igates an inter nal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the ris - ing edge. when 16/68# pin is low, the motorola bus interface is selected and this input is not used. iow# (r/w#) 12 15 f2 i when 16/68# pin is high, it selects intel bus interface and this input becomes write strobe (active low). the fall - ing edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an inter - nal register pointed by the address lines. when 16/68# pin is low, the motorola bus interface is selected and this input becomes read (high) and write (low) signal. csa# (cs#) 7 10 e2 i when 16/68# pin is high, this input is chip select a (active low) to enable channel a in the device. when 16/68# pin is low, this input becomes the chip select (active low) for th e motorola bus interface. csb# (a3) 8 11 e1 i when 16/68# pin is high, this input is chip select b (active low) to enable channel b in the device. when 16/68# pin is low, this input becomes address line a3 which is used for channel selection in the motor - ola bus interface. input logic 0 selects channel a and logic 1 selects channel b.
xr16m752/xr68m752 5 rev. 1.1.1 high performance duart with 64-byte fifo inta (irq#) 22 30 d6 o when 16/68# pin is high for intel bus interface, this out - put becomes channel a interrupt output. the output state is defined by the user through the software setting of mcr[3]. inta is set to the active mode and op2a# out - put low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to high when mcr[3] is set to a logic 0. see mcr[3]. when 16/68# pin is low for motorola bus interface, this output becomes device interrupt output (active low, open drain). an external pull-up resistor is required for proper operation. intb (nc) 21 29 d7 o when 16/68# pin is high for intel bus interface, this out - put becomes channel b interrupt output. the output state is defined by the user through the software setting of mcr[3]. intb is set to the active mode and op2a# out - put to low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to high when mcr[3] is set to a logic 0. see mcr[3]. when 16/68# pin is low for motorola bus interface, this output is not used. txrdya# - 43 c4 o uart channel a transmitter ready (active low). the output provides the tx fifo /thr status for transmit channel a. see table 3 . if it is not used, leave it uncon - nected. rxrdya# - 31 e5 o uart channel a receiver ready (active low). this out - put provides the rx fifo/rhr status for receive channel a. see table 3 . if it is not used, leave it unconnected. txrdyb# - 6 d4 o uart channel b transmitter ready (active low). the output provides the tx fifo /thr status for transmit channel b. see table 4 . if it is not used, leave it uncon - nected. rxrdyb# - 18 f4 o uart channel b receiver ready (active low). this out - put provides the rx fifo/rhr status for receive channel b. see table 3 . if it is not used, leave it unconnected. modem or serial i/o interface txa 5 7 d3 o uart channel a transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high dur - ing reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is lo w. if it is not used, leave it unconnected. pin description n ame 32-qfn p in # 48-tqfp p in # 49-stbga p in # t ype d escription
xr16m752/xr68m752 6 high performance duart with 64-byte fifo rev. 1.1.1 rxa 4 5 d2 i uart channel a receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pulses typically idles at low but can be inverted by software control prior going in to the decoder, see mcr[6]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsa# 23 33 d5 o uart channel a request-to-send (active low) or general purpose output. this output must be asserted prior to using auto rts flow control, see efr[6] and ier[6]. for auto rs485 half-duplex dire ction control, see dld[6]. ctsa# 25 38 a5 i uart channel a clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7] and ier[7]. this input should be connected to vcc or gnd when not used. dtra# - 34 a7 o uart channel a data-terminal-ready (active low) or general purpose output. if it is not used, leave it uncon - nected. dsra# - 39 b6 i uart channel a data-set-ready (active low) or general purpose input. this input should be connected to vcc or gnd when not used. cda# - 40 c5 i uart channel a carrier-detect (active low) or general purpose input. this input should be connected to vcc or gnd when not used. ria# - 41 a4 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc or gnd when not used. op2a# - 32 c6 o output port 2 channel a - the output state is defined by the user and through the soft ware setting of mcr[3]. inta is set to the active mode and op2a# output low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# output high when mcr[3] is set to a logic 0. see mcr[3]. if inta is used, this output should not be used as a general output else it will disturb the inta output functionality. txb 6 8 d1 o uart channel b transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high dur - ing reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is lo w. if it is not used, leave it unconnected. rxb 3 4 c3 i uart channel b receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pulses typically idles at logic 0 but can be inverted by software control prior going in to the decoder, see mcr[6]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. pin description n ame 32-qfn p in # 48-tqfp p in # 49-stbga p in # t ype d escription
xr16m752/xr68m752 7 rev. 1.1.1 high performance duart with 64-byte fifo rtsb# 15 22 g5 o uart channel b request-to-send (active low) or general purpose output. this port must be asserted prior to using auto rts flow control, see efr[6] and ier[6]. for auto rs485 half-duplex directio n control, see dld[6]. ctsb# 16 23 f6 i uart channel b clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7] and ier[7]. this input should be connected to vcc or gnd when not used. dtrb# - 35 c7 o uart channel b data-terminal-ready (active low) or general purpose output. if it is not used, leave it uncon - nected. dsrb# - 20 f5 i uart channel b data-set-ready (active low) or general purpose input. this input should be connected to vcc or gnd when not used. cdb# - 16 f3 i uart channel b carrier-detect (active low) or general purpose input. this input should be connected to vcc or gnd when not used. rib# - 21 e4 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc or gnd when not used. op2b# - 9 e3 o output port 2 channel b - the output state is defined by the user and through the soft ware setting of mcr[3]. intb is set to the active mode and op2b# output low when mcr[3] is set to a logic 1. intb is set to the three state mode and op2b# output high when mcr[3] is set to a logic 0. see mcr[3]. if intb is used, this output should not be used as a general output else it will disturb the intb output functionality. ancillary signals xtal1 10 13 g1 i crystal or external clock input. xtal2 11 14 g2 o crystal or buffered clock output. pwrsave - - f1 i powersave (active high, internal pull-down resistor). this feature isolates the 752?s dat a bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. see sleep mode with auto wake-up and powersave feature section for details. 16/68# 17 24 g6 i intel or motorola bus select (internal pull-up resistor). this pin is not available for the xr16m752. this pin is available for the xr68m752 only. when 16/68# pin is high, 16 or intel mode, the device will operate in the intel bus type of interface. when 16/68# pin is low, 68 or motorola mode, the device will operate in the moto rola bus type of interface. pin description n ame 32-qfn p in # 48-tqfp p in # 49-stbga p in # t ype d escription
xr16m752/xr68m752 8 high performance duart with 64-byte fifo rev. 1.1.1 pin type: i=input, o=output, i/o= input/output, od=output open drain. reset (reset#) 24 36 b7 i when 16/68# pin is high for intel bus interface, this input becomes reset (active high ). when 16/68# pin is low for motorola bus interface, this input becomes reset# (active low). a 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of channel a and b. the uart transmitter output will be held high, the receiver input will be ignored and outputs are reset during reset period (see table 16 ). en485# - - a6 i auto rs-485 half-duplex direction output enable for channel a and b (active low, internal pull-up resistor). connect this pin to vcc or leave unconnected for normal rts# a/b function. connect to gnd for auto rs-485 half-duplex direction output via the rts# a/b pins. the auto rs-485 half-duplex dire ction output control feature can be disabled via dld[6] after power-up. see ?auto rs485 half-duplex control? on page 18. enir# - - f7 i ir mode enable for channel a and b (active low, internal pull-up resistor). connect this pin to vcc or leave uncon - nected for normal tx and rx. connect to gnd for both channel a and b to power up in the ir mode. the ir mode can be disabled via dld[7] after power-up. see ?infrared mode? on page 20. vcc 26 42 b5 pwr 1.62v to 3.63v power supply. gnd 13 17 g3 pwr power supply common, ground. gnd center pad - - pwr the center pad on the ba ckside of the qfn package is metallic and should be conn ected to gnd on the pcb. the thermal pad size on the pcb should be the approxi - mate size of this center pad and should be solder mask defined. the solder mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. nc 9 12, 25, 37 a1 no connection. pin description n ame 32-qfn p in # 48-tqfp p in # 49-stbga p in # t ype d escription
xr16m752/xr68m752 9 rev. 1.1.1 high performance duart with 64-byte fifo 1.0 product description the xr16m752/xr68m752 (m752) integrates the functi ons of 2 enhanced 16c550 universal asynchronous receiver and transmitter (uart). each uart is i ndependently controlled having its own set of device configuration registers. the configuration registers set is 16550 uart compatible for control, status and data transfer. additionally, each uart channel has 64-bytes of transmit and receive fifos, automatic rts/cts hardware flow control, automatic xon/ xoff and special character software flow control, programmable transmit and receive fifo trigger levels, infrared encoder and decoder (irda ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 mbps with 4x sampling clock rate. the xr16m752 is a 1.62v to 3.63v device. the m752 is fabricated with an advanced cmos process. enhanced features the m752 duart provides a solution that supports 64 by tes of transmit and receive fifo memory, instead of 16 bytes in the industry standard 16c550. the m752 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. increased performance is realized in the m752 by the larger transmit and receiv e fifos, fifo trigger level control and automatic flow control mechanism. this allows the external processor to ha ndle more networking ta sks within a given time. for example, the 16c550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, includin g start/stop bits at 115.2 kbps). th is means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 64 byte fifo in the m752, the data buffer will not require unloading/loading for 6.1 ms. this increases the service interval giving the external cpu additional time for other applications and re ducing the overall uart interrupt servicing time. in addition, the programmable fifo level trigger interrupt and automatic hardware/software flow cont rol is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. the combination of the above greatly reduces the cpu?s bandwidth requirement, increases performance, and reduces power consumption. the m752 supports a half-duplex output direction contro l signaling pin, rts# a/b, to enable and disable the external rs-485 transceiver operation. it automatically s witches the logic state of th e output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. after receiving, the logic state of the output pin switches back to the transmit st ate when a data byte is loaded in the transmitter. the auto rs-485 direction control pin is no t activated after reset. to activate the direction control function, user has to set dld bit-6 to ?1?. this pin is high for receive state and low for transmit state. data rate the m752 is capable of operation up to 16 mbps at 3.3v with 4x internal sampling clock rate, 8 mbps at 3.3v with 8x sampling clock rate, and 4 mbps at 3.3v with 16x internal sampling clock rate. the device can operate with an external 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 64 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit for data rates of up to 3.68 mbps. the rich feature set of the m752 is available through th e internal registers. automatic hardware/software flow control, programmable transmit and receive fifo trigge r levels, programmable tx and rx baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. following a power on reset or an external reset, the m7 52 is software compatible with previous generation of uarts, 16c450, 16c550 and 16c2550.
xr16m752/xr68m752 10 high performance duart with 64-byte fifo rev. 1.1.1 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the xr16m752 data interface supports the intel compatible types of cpus while the xr68m752 supports both the intel and motorola co mpatible data interfaces. no clock (oscillator nor external clock) is required to operate a data bus transaction. each bus cycle is asynchronous using cs#, ior# and iow# signals. both uart channels share the same data bus for host operations. the data bus interconnections are shown in figure 4 . f igure 4. xr16m752/xr68m752 d ata b us i nterconnections vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# uart_reset reset serial interface of rs-232, rs-422 or rs-485 serial interface of rs-232, rs-422 or rs-485 (no connect) (no connect) 2.25 to 3.6 volt vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_irq# intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# reset# vcc uart_reset# (no connect) (no connect) (no connect) vcc intel data bus interconnections motorola data bus interconnections serial interface of rs-232, rs-422 or rs-485 serial interface of rs-232, rs-422 or rs-485
xr16m752/xr68m752 11 rev. 1.1.1 high performance duart with 64-byte fifo 2.2 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see table 16 ). an active high pulse of l onger than 40 ns duration will be required to activate the reset function in the device. 2.3 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. during intel bus mode (16/68# pin connected to vcc), a logic 0 on chip select pins, csa# or csb#, allows the us er to select uart channel a or b to configure, send transmit data and/or unload receive data to/from the ua rt. selecting both uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from both uarts simultaneously. individual channel select functions are shown in table 1 . t able 1: c hannel a and b s elect in 16 m ode f unction 1 1 uart de-selected 0 1 channel a selected 1 0 channel b selected 0 0 channel a and b selected during motorola bus mode (16/68# pin connected to gnd), the package interface pins are configured for connection with motorola, and other popular microproce ssor bus types. in this mode the m752 decodes an additional address, a3, to select one of the uart ports. the a3 address decode function is used only when in the motorola bus mode. see table 2 . t able 2: c hannel a and b s elect in 68 m ode f unction 1 n/a uart de-selected 0 0 channel a selected 0 1 channel b selected 2.4 channel a and b internal registers each uart channel in the m752 has a set of enhanced r egisters for control, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550 and dual st16c2550. these r egisters function as data holding regi sters (thr/rhr), interrupt status and control registers (isr/ier), a fi fo control register (fcr), receive lin e status and control registers (lsr/ lcr), modem status and control regist ers (msr/mcr), programmable data rate (clock) divisor registers (dll/ dlm/dld), and a user accessible scratchpad register (spr). beyond the general 16c55 0 features and capab ilities, the m752 offers enhanced feature registers (efr, xon/ xoff 1, xon/xoff 2, tcr, tlr and dld) that provide automatic rts and cts hardware flow control, xon/xoff software flow control, automatic rs-485 half-duplex direction output enable/dis able, and programmable fifo trigger level control. all the register func tions are discussed in full detail later in ?section 3.0, uart internal registers? on page 24 . csa# csb# cs# a3
xr16m752/xr68m752 12 high performance duart with 64-byte fifo rev. 1.1.1 2.5 dma mode the device does not support direct me mory access. the dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the m752 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by th e programmed trigger level. in this mode, the m752 sets the txrdy# pin when the transmit fifo becomes fu ll, and sets the rxrdy# pin when the receive fifo becomes empty. the following table shows their behavior. also see figures 20 through 25 . t able 3: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# a/b low = 1 byte. high = no data. low = at least 1 byte in fifo. high = fifo empty. high to low transition when fifo reaches the trigger level, or time-out occurs. low to high transition when fifo empties or lsr[7] = 1. txrdy# a/b low = thr empty. high = byte in thr. low = fifo empty. high = at least 1 byte in fifo. low = fifo is below the trigger level. high = fifo is full. 2.6 inta and intb outputs the inta and intb interrupt output changes according to the operating mode and enhanced features setup. table 4 and 5 summarize the operating behavior for the transmitter and receiver. also see figures 20 through 25 . t able 4: inta and intb p ins o peration for t ransmitter auto rs485 mode fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin no low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty inta/b pin yes low = a byte in thr high = transmitter empty low = fifo above trigger level high = fifo below trigger level or transmitter empty t able 5: inta and intb p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level
xr16m752/xr68m752 13 rev. 1.1.1 high performance duart with 64-byte fifo 2.7 crystal oscillator or external clock input the m752 includes an on-chip oscillator (xtal1 and xtal2) to pro duce a clock for both uart sections in the device. the cpu data bus does not r equire this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer i nput with xtal2 pin being the output. pleas e note that the i nput xtal1 is not 5v tolerant and so the maximum at the pin should be vcc. for programming details, see ? ?section 2.8, programmable baud rate generator with fractional divisor? on page 13 .? f igure 5. t ypical oscillator connections c1 22-47 pf c2 22-47 pf y1 1.8432 mhz to 24 mhz r1 0-120 ? (optional) r2 500 ? ? 1 ? xtal1 xtal2 the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 5 ). the programmable baud rate generator is capable of operating with a crystal osc illator frequency of up to 24 mhz. however, with an external clock input on xtal1 pin, it can extend its oper ation up to 64 mhz (16 mbps serial data rate) at 3.3v with an 4x sampling rate. for further reading on the oscillator circuit plea se see the applicat ion note dan108 on the exar web site at http://www.exar.com. 2.8 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the outpu t of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16x, 8x or 4x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (d ll, dlm and dld registers) defaults to the value of ?1? (dll = 0x01, dlm = 0x00 and dld = 0x00) upon reset. therefore, the brg must be programmed during initialization to the operating data rate. the dll and dlm registers provide the integer part of the divisor and the dld register provides the fraction al part of the dvisior. the four lowe r bits of the dld are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). programming the baud rate generator registers dll, dlm and dld provides the capa bility for selecting the operating data rate. table 6 shows the standard data rates available with a 24mhz crystal or extern al clock at 16x clock rate. if the pre-scaler is used (mcr bit-7 = 1), the output data rate will be 4 times less than that shown in table 6 . at 8x sampling rate, these data rates would double and at 4x sampling rate, these data rates would quadruple. also, when using 8x sampling mode, the bit time will have a jitter of 1/16 whenever the dld is non-zero and is an odd number.
xr16m752/xr68m752 14 high performance duart with 64-byte fifo rev. 1.1.1 when using 4x sampling mode, th e bit time will have a jitter of 1/8 whenever dld is non-zero, odd and not a multiple of 4. when using a non-standard data rate crystal or exte rnal clock, the divisor value can be calculated with the following equation(s): required divisor (decimal)=(xtal1 clock frequency / pre scaler) /(serial data rate x 16), with 16x mode, dld[5:4]=?00? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8x mode, dld[5:4] = ?01? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 4), with 4x mode, dld[5:4] = ?10? round( (required divisor - trunc(required divisor ) )*16)/16 + trunc( required divisor), where dlm = trunc(required divisor) >> 8 dll = trunc(required divisor) & 0xff dld = round( (required divisor -trunc(required divisor) )*16) the closest divisor that is obtainable in the m752 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10. a >> b indicates right shifting the value ?a? by ?b? number of bits. for example, 0x78a3 >> 8 = 0x0078. f igure 6. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x or 8x or 4x sampling rate clock to transmitter and receiver to other channel fractional baud rate generator logic
t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling required output data rate d ivisor for 16x clock (decimal) d ivisor o btainable in m752 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex) d ata e rror r ate (%) 400 3750 3750 e a6 0 0 2400 625 625 2 71 0 0 4800 312.5 312 8/16 1 38 8 0 9600 156.25 156 4/16 0 9c 4 0 10000 150 150 0 96 0 0 19200 78.125 78 2/16 0 4e 2 0 25000 60 60 0 3c 0 0 28800 52.0833 52 1/16 0 34 1 0.04 38400 39.0625 39 1/16 0 27 1 0 50000 30 30 0 1e 0 0 57600 26.0417 26 1/16 0 1a 1 0.08 75000 20 20 0 14 0 0 100000 15 15 0 f 0 0 115200 13.0208 13 0 d 0 0.16 153600 9.7656 9 12/16 0 9 c 0.16 200000 7.5 7 8/16 0 7 8 0 225000 6.6667 6 11/16 0 6 b 0.31 230400 6.5104 6 8/16 0 6 8 0.16 250000 6 6 0 6 0 0 300000 5 5 0 5 0 0 400000 3.75 3 12/16 0 3 c 0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 0 0 750000 2 2 0 2 0 0 921600 1.6276 1 10/16 0 1 a 0.16 1000000 1.5 1 8/16 0 1 8 0 xr16m752/xr68m752 15 rev. 1.1.1 high performance duart with 64-byte fifo 2.9 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 64 bytes of fifo which includes a byte-wide transmit holding register (thr) . tsr shifts out every data bit with the 16x/8x/4x internal clock. a bit time is 16 (8 if 8x or 4 if 4x) clock periods (see dld[5:4]). the transmitter sends the start- bit followed by the number of data bits, inserts the prop er parity-bit if enabled, and adds the stop-bit(s). the status of the fifo and tsr are reported in the line status register (lsr[6:5]).
xr16m752/xr68m752 16 high performance duart with 64-byte fifo rev. 1.1.1 2.9.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 64 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.9.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. f igure 7. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x or 4x clock ( dld[5:4] ) 2.9.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 64 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed tr igger level. the transmit em pty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x or 4x clock ( dld[5:4] ) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.) txfifo1
xr16m752/xr68m752 17 rev. 1.1.1 high performance duart with 64-byte fifo 2.10 receiver the receiver section contains an 8-bit receive shift register (rsr) and 64 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x/8x/4x clock (dld [5:4]) for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x/8x/4x clock rate. after 8 clocks (or 4 if 8x or 2 if 4x) the start bit pe riod should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if th ere were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the rece ive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay unti l it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data read y time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.10.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 64 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) receive data characters data bit validation error tags in lsr bits 4:2
f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) error tags (64-sets) error tags in lsr bits 4:2 receive data characters fifo trigger=16 example : - rx fifo trigger level selected at 16 bytes (see note below) data fills to halt level data falls to resume level data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills to the halt level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls to the resume level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1. 64 bytes by 11-bit wide fifo xr16m752/xr68m752 18 high performance duart with 64-byte fifo rev. 1.1.1 2.11 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 11 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.12 auto rts halt and resume the rts# pin will not be forced high (rts off) until the receive fifo r eaches the halt leve l (tcr[3:0]). the rts# pin will return low after the rx fifo is unl oaded to the resume leve l (tcr[7:4]). under these conditions, the m752 will continue to accept data if the remote ua rt continues to transmit data. it is the responsibility of the user to ensure t hat the halt level is greater than th e resume level. if interrupts are used, it is recommended that halt level > rx trigger level > resume level. t he auto rts function is initiated when the rts# output pin is asserted low (rts on). 2.13 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by dld bit-6. when idle, the auto rs485 half-duplex direction control signal (rts#) is low for receive mode. when data is loaded into the thr for transmission, the rts# output is automatically assert ed high prior to sending the data. after the last stop bit of th e last character that has been transmitted, the rts# signal is automatically de-asserted. this helps in turning around the transceiver to receive the remote station?s response. when the host is ready to tran smit next polling data packet, it only has to load data bytes to th e transmit fifo. the transmitter automatically re-asserts rts# (high) output pr ior to sending the data. in addition to changing the behavior of the rts# output, this feature also chang es the behavior of the transmit empty interrupt (see table 4 ). in the 49-pin stbga package, this feature can be enabled by connecting the en485# pin to gnd. if this feature is enabled by the en485# pin, it can be disabled by dld bit-6 after power-up.
xr16m752/xr68m752 19 rev. 1.1.1 high performance duart with 64-byte fifo 2.14 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 11 ): ? enable auto cts flow control using efr bit-7. if using the auto cts interrupt: ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high): is r bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (low), indicating more data may be sent. f igure 11. a uto rts and cts f low c ontrol o peration rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1 the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow.
xr16m752/xr68m752 20 high performance duart with 64-byte fifo rev. 1.1.1 2.15 auto xon/xoff (software) flow control when software flow control is enabled ( see table 15 ), the m752 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the m752 will halt transmission (tx) as soon as th e current characte r has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a ma tch of the xoff character, the m752 will monitor the receive data stream for a match to t he xon-1,2 character. if a match is found, the m752 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of th e xon/xoff 8-bit flow control registers to 0x00. following reset the user can write any xon/xoff value desired for software flow cont rol. different conditions can be set to detect xon/xoff characters ( see table 15 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the m752 compares two consec utive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissi ons accordingly. under the above described flow control mechanisms, flow control characters are not placed (sta cked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow cont rol needs to be executed , the m752 au tomatically sends the xoff-1,2 via the serial tx output to the re mote modem when the rx fifo reaches the halt level (tcr[3:0]). to clear this condition, the m752 will transmit the programmed xon-1, 2 characters as soon as rx fifo falls down to the resume level. 2.16 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the m752 compares each incoming rece ive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and is r bit-4 will be set to indicate detection of special character. al though the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word lengt h. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. 2.17 infrared mode the m752 uart includes the infrared encoder and decoder compatible to the irda (i nfrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on- time of the infrared led, hence reduces the power consumption. see figure 12 below. the infrared encoder and decoder can be enabled by setting dld register bit-7 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles low. likewise, the rx input also idles low, see figure 12 . in the 49-pin stbga package, this feature can be enabled upon power-up by connecting the enir# pin of the stbga package to gnd. if the ir mo de is enabled via the enir# pin, it can be disabled after power-up via dld bit-7. the wireless infrared decoder receives the input pulse fr om the infrared sensing diode on the rx pin. each time it senses a light pulse, it retu rns a logic 1 to the data bit stream.
xr16m752/xr68m752 21 rev. 1.1.1 high performance duart with 64-byte fifo f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16m752/xr68m752 22 high performance duart with 64-byte fifo rev. 1.1.1 2.18 sleep mode with wake-up indicator and powersave feature the m2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and powersave feature is included to reduce power consumption when the device is not actively used. 2.19 sleep mode with auto wake-up the m752 supports low voltage system designs, he nce, a sleep mode is included to reduce its power consumption when the chip is not actively used. in addition, there is a powersave feature on the 49-pin stbga package that eliminates any unnecessary external buffer. all of these conditions must be satisf ied for the m752 to enter sleep mode: no interrupts pending for both channels of the m752 (isr bit-0 = 1) sleep mode of both channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pins are idling high the m752 stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the m752 resumes normal operation by any of the following: a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the m752 is awakened by any one of the above conditio ns, it will return to the sle ep mode automatically after all interrupting conditions have been serviced and cleared. if the m752 is awak ened by the modem inputs, a read to the msr is required to re set the modem inputs. in any case, t he sleep mode will not be entered while an interrupt is pending from channel a or b. the m752 will stay in the sl eep mode of operat ion until it is disabled by setting ier bit-4 to a logic 0. if the address lines, data bus lines, iow#, ior#, csa#, csb#, and modem input lines remain steady when the m752 is in sleep mode , the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 40 . if the input lines are floating or are toggling while the m752 is in sleep mode, the current can be up to 100 times more. if any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. 2.19.1 powersave feature (49-pin stbga pacakge only) the powersave feature will eliminate t he need for an external buffer by in ternally isolatin g the address, data and control signals from other bus activities that could cause wasteful power drain. the m752 enters powersave mode when pin f1 is connected to vcc and th e m752 is in sleep mode (see sleep mode section above). since powersave mode isolates the address, data and control signals, the device will wake-up by: a receive data start bit transition (high to low) a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# the m752 will return to th e powersave mode automatically after a read to the msr (t o reset the modem inputs) and all interrupting conditions have been serv iced and cleared. the 2751 will stay in the powersave mode of operation until it is disabled by setting ier bit-4 to a logic 0 and/or the powersave pin is connected to gnd. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. the number of ch aracters lost during the restart also depends on your operating data rate. more characters are lost when operati ng at higher data rate. also, it is important to keep rx a/b inputs idling high or ?mar king? condition during sleep mode to avoid receiving a ?break? condition upon the restart. this may occur when the external inte rface transceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the ?mar king? condition. to avoid this, the designer can use a 47k-100k ohm pull-up resistor on the rxa and rxb pins.
xr16m752/xr68m752 23 rev. 1.1.1 high performance duart with 64-byte fifo 2.20 internal loopback the m752 uart provides an inter nal loopback capability for system diagnostic purposes. the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 13 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx, rts# and dtr# pins are held while the cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input pin must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. also , auto rts/cts flow control is not supported during internal loopback. f igure 13. i nternal l oop b ack in c hannel a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb# dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2a#/op2b#
xr16m752/xr68m752 24 high performance duart with 64-byte fifo rev. 1.1.1 3.0 uart internal registers each of the uart channel in the m752 has its own set of configuration registers selected by address lines a0, a1 and a2 with csa# or csb# selecting the channel. the complete register set is shown on table 7 and table 8 . t able 7: uart channel a and b uart internal registers a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - divisor msb read/write 0 1 0 dld - divisor fractional read/write lcr[7] = 1, lcr 0xbf, efr[4] = 1 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr 0xbf 1 0 1 lsr - line status register read-only 1 1 0 msr - modem status register read-only see table 13 1 1 1 spr - scratch pad register read/write see table 12 1 1 0 tcr - transmission control register read/write see table 13 1 1 1 tlr - trigger level register read/write see table 12 1 1 1 fifo rdy - fifo ready register read-only see table 12 e nhanced r egisters 0 1 0 efr - enhanced function register read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write a2 a1 a0
xr16m752/xr68m752 25 rev. 1.1.1 high performance duart with 64-byte fifo . t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/ int out - put enable fifo rdy enable (op1#) rts# output control dtr# output control lcr z 0xbf clock pres - caler select tcr and tlr enable xonany 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx framing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# see table 13 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 see table 12 1 1 0 tcr rd/wr resume bit-3 resume bit-2 resume bit-1 resume bit-0 halt bit-3 halt bit-2 halt bit-1 halt bit-0 see table 13 1 1 1 tlr rd/wr rx trig bit-3 rx trig bit-2 rx trig bit-1 rx trig bit-0 tx trig bit-3 tx trig bit-2 tx trig bit-1 tx trig bit-0 see table 12 1 1 1 fifo rdy rd 0 0 rx fifo b status rx fifo a status 0 0 tx fifo b status tx fifo a status see table 12
xr16m752/xr68m752 26 high performance duart with 64-byte fifo rev. 1.1.1 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see ?receiver? on page 17. 4.2 transmit holding register (thr) - write-only see ?transmitter? on page 15. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr z 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 1 0 dld rd/wr ir mode auto rs485 direction control 4x mode 8x mode bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr z 0xbf efr[4]=1 enhanced registers 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5], dld soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0 x bf 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff 1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff 2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16m752/xr68m752 27 rev. 1.1.1 high performance duart with 64-byte fifo 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16m752 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. x logic 0 = disable the receive data ready interrupt (default). x logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when spaces in the fifo is above the pr ogrammed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. x logic 0 = disable transmit ready interrupt (default). x logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bit-7 is set if any character in the rx fifo has a parity or framing error, or is a break character. lsr[4:2] always show the error stat us for the received character available for reading from the rx fifo. if ier[2] = 1, an ls r interrupt will be generated as long as lsr[7] = 1, ie . the rx fifo contains at lease one character with an error. x logic 0 = disable the receiver line status interrupt (default). x logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable x logic 0 = disable the modem status register interrupt (default). x logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) x logic 0 = disable sleep mode (default). x logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr bit-4=1) x logic 0 = disable the software flow cont rol, receive xoff interrupt (default). x logic 1 = enable the receive xoff interrupt. see software flow control section for details.
xr16m752/xr68m752 28 high performance duart with 64-byte fifo rev. 1.1.1 ier[6]: rts# output interrupt enable (requires efr bit-4=1) x logic 0 = disable the rts# interrupt (default). x logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) x logic 0 = disable the cts# interrupt (default). x logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: x lsr is by any of the lsr bits 1, 2, 3, 4 and 7. x rxrdy is by rx trigger level. x rxrdy time-out is by a 4-char plus 12 bits delay timer. x txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). x msr is by any of the msr bits 0, 1, 2 and 3. x receive xoff/special character is by det ection of a xoff or special character. x cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control. x rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. 4.4.2 interrupt clearing: x lsr interrupt is cleared by reading all characters with errors out of the rx fifo. x rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. x rxrdy time-out interrupt is cleared by reading rhr. x txrdy interrupt is cleared by a read to the isr register or writing to thr. x msr interrupt is cleared by a read to the msr register. x xoff interrupt is cleared when xon character(s) is received. x special character interrupt is cleared by a read to isr. x rts# and cts# flow control interrupts are cleared by a read to the msr register.
xr16m752/xr68m752 29 rev. 1.1.1 high performance duart with 64-byte fifo ] t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 9 ). isr[4]: xoff/xon or special character interrupt status this bit is set when efr[4] = 1 and ier[5] = 1. isr bit- 4 indicates that the receiver detected a data match of the xoff character(s). if this is an xoff interrupt, it is cleared when xon is received. if it is a special character interrupt, it is cleared by reading isr. isr[5]: rts#/cts# interrupt status this bit is enabled when efr[4] = 1. isr bit-5 indicates that the cts# or rts# has been de-asserted. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed.
xr16m752/xr68m752 30 high performance duart with 64-byte fifo rev. 1.1.1 fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (requires efr bit-4=1) (logic 0 = default, tx trigger level = 8) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of spaces in the fifo is above the selected trigge r level, or when it gets em pty in case that the fifo did not get filled over the trig ger level on last re-load. table 10 shows the selections. the uart will issue a transmit interrupt when the number of available spaces in the fifo is less than the transmit tr igger level. table 10 shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level = 8) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in t he fifo is greater than the receive trigger level or when a receive data timeout occurs (see ?section 2.10, receiver? on page 17 ). t able 10: t ransmit and r eceive fifo t rigger l evel s election b it -7 b it -6 b it -5 bit -4 r eceive t rigger l evel ( characters ) t ransmit t rigger l evel ( spaces ) 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 fcr fcr fcr fcr
xr16m752/xr68m752 31 rev. 1.1.1 high performance duart with 64-byte fifo 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. w ord length 0 0 5 0 1 6 (default) 1 0 7 1 1 8 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 (default) lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated duri ng the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 bit-2
xr16m752/xr68m752 32 high performance duart with 64-byte fifo rev. 1.1.1 lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0? lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space", low state). this condition remains, unt il disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?spa ce?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll, dlm and dld) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for contro lling the serial/modem interface signal s or general pur pose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. the rts# pin can also be used for auto rs485 half-duplex direction control enabled by fctr bit- 3. if the modem interface is not used, this out put may be used as a general purpose output. ? logic 0 = force rts# high (default). ? logic 1 = force rts# low.
xr16m752/xr68m752 33 rev. 1.1.1 high performance duart with 64-byte fifo mcr[2]: op1# / fifo rdy enable op1# is not available as an output pin on the m752. but it is available for use during internal loopback mode (mcr[4] = 1). in the in ternal loopback mode, this bit is used to write the state of the modem ri# interface signal. this bit is also used to select between the spr, tlr and fifo rdy registers. all of these registers are accessible at address offset 0x7 when lcr 0xbf . however, lcr = 0xbf is required to access efr. t able 12: r egister at a ddress o ffset 0 x 7 efr[4] mcr[6] mcr[4, 2] register at address offset 0x7 0 x ?01? scratchpad register (spr) 1 0 ?01? scratchpad register (spr) 1 1 ?01? trigger level register (tlr) x x =?01? fifo ready register (fifo rdy) mcr[3]: op2# output / int output enable this bit enables or disables the operation of int, interr upt output. if int output is not used, op2# can be used as a general purpose output. ? logic 0 = int (a-b) outputs disabled (three stat e mode) and op2# output set high(default). ? logic 1 = int (a-b) outputs enabled (active mode) and op2# output set low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 13 . mcr[5]: xon-any enable (requires efr bit-4=1 to write to this bit) ? logic 0 = disable xon-any function (default). ? logic 1 = enable xon-any function. in this mode, any rx character re ceived will resume transmit operation. the rx character will be loaded into the rx fifo, unless the rx characte r is an xon or xo ff character and the m752 is programmed to use the xon/xoff flow control. mcr[6]: tcr and tlr enable (requires efr bit-4=1 to write to this bit) this bit enables the tcr and tlr registers at address offset 0x6 and 0x7, respectively. see table 12 above for the correct register setting to access the tlr register. see table 13 below for the setting to access the tcr register. ? logic 0 = reserved (default). ? logic 1 = enable access to the tcr and tlr registers. t able 13: r egister at a ddress o ffset 0 x 6 efr[4] mcr[6] register at address offset 0x6 0 x modem status register (msr) 1 0 modem status register (msr) 1 1 trigger control register (tcr)
xr16m752/xr68m752 34 high performance duart with 64-byte fifo rev. 1.1.1 mcr[7]: clock prescaler select (requires efr bit-4=1 to write to this bit) x logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). x logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator x logic 0 = no data in receive holding register or fifo (default). x logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag x logic 0 = no overrun error (default). x logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag x logic 0 = no parity error (default). x logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error tag x logic 0 = no framing error (default). x logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag x logic 0 = no break condition (default). x logic 1 = the receiver received a break signal (rx wa s low for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag x logic 0 = no fifo error (default). x logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem
xr16m752/xr68m752 35 rev. 1.1.1 high performance duart with 64-byte fifo changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag x logic 0 = no change on cts# input (default). x logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag x logic 0 = no change on dsr# input (default). x logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag x logic 0 = no change on ri# input (default). x logic 1 = the ri# input has changed from a low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag x logic 0 = no change on cd# input (default). x logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow contro l allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will re sume data transmission. normally ms r bit-4 bit is the complement of the cts# input. however in the loopba ck mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loop back mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used.
xr16m752/xr68m752 36 high performance duart with 64-byte fifo rev. 1.1.1 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. there are also two other registers (tlr and fifo rdy) that share th e same address location as the scratch pad register. see table 12 . 4.11 transmission control register (tcr) - read/write (requires efr bit-4 = 1) this register replaces msr and is access ible only when mcr[6] = 1. this 8- bit register is used to store the rx fifo threshold levels to halt/res ume transmission during hardware or software flow control. tcr[3:0]: rx fifo halt level a value of 0-60 (decimal value of tcr[3:0] multiplied by 4) can be selected as the halt level. when the rx fifo is greater than or equal to this value, the rts# output will be de-asserted if auto rts flow control is used or the xoff character(s) will be transmitted if auto xo n/xoff flow control is used . it is recommended that this value is greater than the rx trigger level. tcr[7:4]: rx fifo resume level a value of 0-60 (decimal value of tcr[7:4] multiplied by 4) can be selected as the resume level. when the rx fifo is less than or equal to this value, the rts# output will be re-assert ed if auto rts flow control is used or the xon character(s) will be transmitted if auto xon/xo ff flow control is used. it is recommended that this value is less than th e rx trigger level. 4.12 trigger level register (tlr) - read/write (requires efr bit-4 = 1) this register replaces spr and is a ccessible under the conditions listed in table 12 . this 8-bit register is used to store the rx and tx fifo trigger levels used for interrupts. tlr[3:0]: tx fifo trigger level a value of 4-60 (decimal value of tcr[3:0] multiplied by 4) can be selected as the tx fifo trigger level. when the number of available spaces in the tx fifo is greater than or equal to this value, a transmit ready interrupt is g enerated. for an y non-zero value, tcr[3:0] will be used as the tx fifo trigger level. if tcr[3:0] = 0x0, then the tx fi fo trigger level is the value selected by fcr[5:4]. see table 10 . tlr[7:4]: rx fifo trigger level a value of 4-60 (decimal value of tcr[7:4] multiplied by 4) can be selected as the rx fifo trigger level. when the number of characters received in the rx fifo is greater than or equal to this value, a receive data ready interrupt is generated (a rece ive data timeout interrupt is independent of the rx fifo trigger level and can be generated any time there is at least 1 byte in the rx fifo and the rx input has been idle for the timeout period described in ?section 2.10, receiver? on page 17 ). for any non-zero value, tcr[7:4] will be used as the rx fifo trigger level. if tcr[7:4] = 0x0, then the rx fifo trigger leve l is the value selected by fcr[7:6]. see table 10 . 4.13 baud rate generator registers (dll, dlm and dld[3:0]) - read/write these registers make-up the value of the baud rate divi sor. the concatenation of the contents of dlm and dll is a 16-bit value is then added to dld[3:0]/16 to achieve the fractional baud rate divisor. dld must be enabled via efr bit-4 before it can be accessed. see ?programmable baud rate generator with fractional divisor? on page 13. dld[5:4]: sampli ng rate select these bits select the data sampling rate. by default, the data sampling rate is 16x. the maximum data rate will double if the 8x mode is selected and will quadruple if th e 4x mode is selected. see table 14 below. t able 14: s ampling r ate s elect dld[5] dld[4] s ampling r ate 0 0 16x
xr16m752/xr68m752 37 rev. 1.1.1 high performance duart with 64-byte fifo dld[6]: auto rs-485 direction control x logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register becomes empty and transmit shift register is shifting data out. the rts# output can be used as a general purpose output or for auto rts flow control. x logic 1 = enable auto rs485 direction control function . the direction control signal, rts# pin, changes its output logic state from high to low on e bit time after the last stop bit of the last character is shifted out. also, the transmit interrupt generation is delayed unt il the transmitter shift register becomes empty. the rts# output pin will automatically re turn to a high when a data byte is loaded into the tx fifo. see ?section 2.13, auto rs485 half-duplex control? on page 18 . dld[7]: infrared en coder/decoder enable x logic 0 = enable the standard modem receive an d transmit input/output interface (default). x logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, the infrared tx ou tput will be idling low. see ?infrared mode? on page 20. 4.14 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 15 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. 0 1 8x 1 x 4x t able 15: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 and xon2, xoff1 and xoff2 t able 14: s ampling r ate s elect dld[5] dld[4] s ampling r ate
xr16m752/xr68m752 38 high performance duart with 64-byte fifo rev. 1.1.1 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, tcr, tlr and dld to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. x logic 0 = modification disable/latch enhanced features. ie r bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5- 7, and dld are saved to retain the user settings. after a reset, the ier bits 4-7, is r bits 4-5, fcr bits 4-5, mcr bits 5-7, and dld are set to a logic 0 to be compatible with st16c550 mode (default). x logic 1 = enables the above-mentioned regist er bits to be modified by the user. efr[5]: special character detect enable x logic 0 = special character detect disabled (default). x logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the pr ogrammed trigge r level and rts de-asserts high at the programmed halt level. rts# will return low when fi fo data falls below the programmed resume level. the rts# output must be asserted (low) before the auto rts can take effect. rts# pin will function as a general purpose out put when hardware flow control is disabled. x logic 0 = automatic rts flow control is disabled (default). x logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. x logic 0 = automatic cts flow control is disabled (default). x logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts high. data transmission resumes when cts# returns low. 4.14.1 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 8 . 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2 t able 15: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol
t able 16: uart reset conditions for channel a and b dlm, dll dlm = 0x00 and dll = 0x01. only resets to these values during a power up. they do not reset when the reset pin is asserted. dld bits 7-0 = 0x00 rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x1d mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff. only resets to thes e values during a power up. they do not reset when the reset pin is asserted. tcr bits 7-0 = 0x0f tlr bits 7-0 = 0x00 fifo rdy bits 7-0 = 0x03 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00. only resets to these values during a power up. they do not reset when the reset pin is asserted. xon2 bits 7-0 = 0x00. only resets to these values during a power up. they do not reset when the reset pin is asserted. xoff1 bits 7-0 = 0x00. only resets to these values during a power up. they do not reset when the reset pin is asserted. xoff2 bits 7-0 = 0x00. only resets to these values during a power up. they do not reset when the reset pin is asserted. i/o signals tx high op2# high rts# high dtr# high rxrdy# high txrdy# low int three-state condition xr16m752/xr68m752 39 rev. 1.1.1 high performance duart with 64-byte fifo registers reset state reset state
xr16m752/xr68m752 40 high performance duart with 64-byte fifo rev. 1.1.1 5.0 electrical characteristics absolute maximum ratings power supply range 4 volts voltage at any pin gnd-0.3v to 4v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error: 15% ) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w thermal resistance (32-qfn) theta-ja = 33 o c/w, theta-jc = 22 o c/w dc electrical characteristics ta= -40 o to +85 o c, vcc is 1.62v to 3.63v s ymbol p arameter l imits m in m ax l imits m in m ax l imits m in m ax u nits c onditions v ilck clock input low level -0.3 0.3 -0.3 0.6 -0.3 0.6 v v ihck clock input high level 1.4 vcc 1.8 vcc 2.4 vcc v v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v v ih input high voltage 1.4 vcc 1.8 vcc 2.0 vcc v v ol output low voltage 0.4 0.4 0.4 v v i ol = 4 ma i ol = 2 ma i ol = 1.5 ma v oh output high voltage 1.4 1.8 2.0 v v i oh = -1 ma i oh = -400 ua i oh = -200 ua i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 0.5 1 2 ma xtal1 = 2 mhz i sleep sleep current (16 mode) 3 10 15 ua see test 1 i sleep sleep current (68 mode) 50 75 100 ua see test 1 test 1: the following inputs must remain steady at vc c or gnd state to minimize sleep current: a0-a2, d0- d7, ior#, iow#, csa# (cs# in 68 mode), csb# and a ll modem inputs. also, rxa a nd rxb inputs must idle high while asleep. floating inputs will result in sleep currents in the ma range. 1.8v 2.5v 3.3v
xr16m752/xr68m752 41 rev. 1.1.1 high performance duart with 64-byte fifo ac electrical characteristics unless otherwise noted: ta=-40 o to +85 o c, vcc=1.62 - 3.63v, 70 pf load where applicable s ymbol p arameter l imits 1.8v 10% m in m ax l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit xtal1 uart crystal oscillator 24 24 24 mhz eclk external clock 32 50 64 mhz t eclk external clock time period 15 10 7 ns t as address setup time (16 mode) 5 5 5 ns t ah address hold time (16 mode) 0 0 0 ns t cs chip select width (16 mode) 60 30 30 ns t rd ior# strobe width (16 mode) 60 30 30 ns t dy read cycle delay (16 mode) 60 30 30 ns t rdv data access time (16 mode) 55 25 25 ns t dd data disable time (16 mode) 0 20 0 20 0 10 ns t wr iow# strobe width (16 mode) 60 30 30 ns t dy write cycle delay (16 mode) 60 30 30 ns t ds data setup time (16 mode) 15 10 10 ns t dh data hold time (16 mode) 5 5 5 ns t ads address setup (68 mode) 5 5 5 ns t adh address hold (68 mode) 0 0 0 ns t rws r/w# setup to cs# (68 mode) 5 5 5 ns t rda read data access (68 mode) 55 25 25 ns t rdh read data disable (68 mode) 20 20 10 ns t wds write data setup (68 mode) 15 10 10 ns t wdh write data hold (68 mode) 5 5 5 ns t rwh cs# de-asserted to r/ w# de-asserted (68 mode) 5 5 5 ns t csl cs# width (68 mode) 60 30 30 ns t csd cs# cycle delay (68 mode) 60 30 30 ns t wdo delay from iow# to output 50 50 50 ns t mod delay to set interrupt from modem input 50 50 50 ns t rsi delay to reset interrupt from ior# 50 50 50 ns t ssi delay from stop to set interrupt 1 1 1 bclk
xr16m752/xr68m752 42 high performance duart with 64-byte fifo rev. 1.1.1 t rri delay from ior# to reset interrupt 45 45 45 ns t si delay from stop to interrupt 45 45 45 ns t int delay from initial int reset to transmit start 8 24 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 45 45 ns t ssr delay from stop to set rxrdy# 1 1 1 bclk t rr delay from ior# to reset rxrdy# 45 45 45 ns t wt delay from iow# to set txrdy# 45 45 45 ns t srt delay from center of start to reset txrdy# 8 8 8 bclk t rst reset pulse width 40 40 40 ns bclk baud clock 16x or 8x or 4x of data rate hz f igure 14. c lock t iming external clock t ech t ecl vih vil t eclk ac electrical characteristics unless otherwise noted: ta=-40 o to +85 o c, vcc=1.62 - 3.63v, 70 pf load where applicable s ymbol p arameter l imits 1.8v 10% m in m ax l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit
f igure 15. m odem i nput /o utput t iming f or c hannels a & b iow # rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active f igure 16. 16 m ode (i ntel ) d ata b us r ead t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd xr16m752/xr68m752 43 rev. 1.1.1 high performance duart with 64-byte fifo
f igure 17. 16 m ode (i ntel ) d ata b us w rite t iming 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr f igure 18. 68 m ode (m otorola ) d ata b us r ead t iming 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data xr16m752/xr68m752 44 high performance duart with 64-byte fifo rev. 1.1.1
f igure 19. 68 m ode (m otorola ) d ata b us w rite t iming 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data t wdh f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) xr16m752/xr68m752 45 rev. 1.1.1 high performance duart with 64-byte fifo
f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) ier[1] enabled f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) xr16m752/xr68m752 46 high performance duart with 64-byte fifo rev. 1.1.1
f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level. xr16m752/xr68m752 47 rev. 1.1.1 high performance duart with 64-byte fifo
f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled xr16m752/xr68m752 48 high performance duart with 64-byte fifo rev. 1.1.1
package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c note: the control dimension is the millimeter column a 0.039 0.047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 xr16m752/xr68m752 49 rev. 1.1.1 high performance duart with 64-byte fifo inches millimeters symbol min max min max
package dimensions (32 pin qfn - 5 x 5 x 0.9 mm ) note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.193 0.201 4.90 5.10 d2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.012 0.020 0.35 0.45 k 0.008 - 0.20 - xr16m752/xr68m752 50 high performance duart with 64-byte fifo rev. 1.1.1
package dimensions (49 pin shrink thin ball grid array - 4 x 4 mm ) b a e d c a1 corner f g 1 32 4 5 76 d1 d1 d d e b a1 a a2 (a1 corner feature is mfger option) plane seating note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.035 0.046 0.88 1.18 a1 0.007 0.011 0.18 0.28 a2 0.028 0.035 0.70 0.90 d 0.154 0.161 3.90 4.10 d1 0.118 bsc 3.00 bsc b 0.010 0.014 0.26 0.36 e 0.020 bsc 0.50 bsc xr16m752/xr68m752 51 rev. 1.1.1 high performance duart with 64-byte fifo
revision history d ate r evision d escription july 2006 p1.0.0 preliminary datasheet. september 2006 1.0.0 final datasheet. updated ac electrical characteristics. may 2007 1.0.1 corrected pin names pin out assignment for 48-pin tqfp package for xr68m752 in motorola mode. added gnd center pad for qfn package to pin description. added motorola mode read/write timing waveforms. updated qfn package dimensions drawing to show minimum "k" parameter. may 2007 1.0.2 updated pin description table, correct pin # of rxa in qfn-32 package. december 2007 1.1.0 added 49-pin stbga package with these additional pins - pwrsave, enir# and en485#. june 2009 1.1.1 corrected page 30 fcr[7:6] and fcr[5:4] default trigger levels. 52 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2008 exar corporation datasheet june 2009. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr16m752/xr68m752 rev. 1.1.1 high performance duart with 64-byte fifo
xr16m752/xr68m752 i rev. 1.1.1 high performance duart with 64-byte fifo table of contents general description........ ................. ................ ................ ............... .............. .......... 1 a pplications ............................................................................................................................... ............... 1 f eatures ............................................................................................................................... ..................... 1 f igure 1. xr16m752 b lock d iagram ............................................................................................................................... ........... 1 f igure 2. p in o ut a ssignment - tqfp and qfn p ackages ....................................................................................................... 2 f igure 3. p in o ut a ssignment - stbga p ackage ...................................................................................................................... 3 ordering information ............................................................................................................................... 3 pin descriptions ............ ................ ................ ................. ................ ................. .......... 4 1.0 product description ........................................................................................................ .............. 9 2.0 functional descriptions .................................................................................................... ........ 10 2.1 cpu interface .............................................................................................................. ................................ 10 f igure 4. xr16m752/xr68m752 d ata b us i nterconnections ................................................................................................ 10 2.2 device reset ........... .............. .............. .............. .............. ........... ........... ........... ........... .................................. 11 2.3 channel a and b selection .......... .............. .............. .............. .............. ........... ........... .......... .................. 11 t able 1: c hannel a and b s elect in 16 m ode .......................................................................................................................... 11 t able 2: c hannel a and b s elect in 68 m ode .......................................................................................................................... 11 2.4 channel a and b internal register s ............. .............. .............. .............. ........... ............ ........... ........ 11 2.5 dma mode ................................................................................................................... .................................... 12 t able 3: txrdy# and rxrdy# o utputs in fifo and dma m ode ........................................................................................... 12 2.6 inta and intb outputs............ .............. .............. .............. .............. ............ ........... ........... ......................... 12 t able 4: inta and intb p ins o peration for t ransmitter ...................................................................................................... 12 t able 5: inta and intb p in o peration f or r eceiver ............................................................................................................. 12 2.7 crystal oscillator or external clock input........... .............. .............. ........... ............ ........... ..... 13 f igure 5. t ypical oscillator connections ............................................................................................................................... 13 2.8 programmable baud rate generator with fractional divisor ........................................... 13 f igure 6. b aud r ate g enerator ............................................................................................................................... ................ 14 t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling ................................................... 15 2.9 transmitter................................................................................................................ .................................. 15 2.9.1 transmit holding register (thr) - write only............................................................................. .............. 16 2.9.2 transmitter operation in non-fifo mode ................................................................................... ................. 16 f igure 7. t ransmitter o peration in non -fifo m ode .............................................................................................................. 16 2.9.3 transmitter operation in fifo mode ....................................................................................... ...................... 16 f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 16 2.10 receiver .................................................................................................................. ..................................... 17 2.10.1 receive holding register (rhr) - read-only .............................................................................. .............. 17 f igure 9. r eceiver o peration in non -fifo m ode .................................................................................................................... 17 f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 18 2.11 auto rts (hardware) flow control .......................................................................................... ...... 18 2.12 auto rts halt and resume ........ .............. .............. .............. .............. ........... ........... ........... ................. 18 2.13 auto rs485 half-duplex control ........................................................................................... .......... 18 2.14 auto cts flow control.................................................................................................... .................... 19 f igure 11. a uto rts and cts f low c ontrol o peration ....................................................................................................... 19 2.15 auto xon/xoff (software) flow control..................................................................................... . 20 2.16 special character detect........ .............. .............. .............. .............. ........... ........... ........... ................. 20 2.17 infrared mode ............................................................................................................. .............................. 20 f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 21 2.18 sleep mode with wake-up indicator and powersave feature ........................................... 22 2.19 sleep mode with auto wake-up ... .............. .............. .............. .............. .............. ........... .......... ............ 22 2.19.1 powersave feature (49-pin stbga pacakge only) ........................................................................... ...... 22 2.20 internal loopback...... .............. .............. .............. .............. .............. .............. .............. ......................... 23 f igure 13. i nternal l oop b ack in c hannel a and b ................................................................................................................ 23 3.0 uart internal registers.................................................................................................... ......... 24 t able 7: uart channel a and b uart internal registers ............................................................................. ......... 24 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 ......................................... 25 4.0 internal register descriptions ............................................................................................. . 26 4.1 receive holding register (rhr) - read- only ......... .............. .............. .............. ............... .............. .. 26 4.2 transmit holding register (thr) - write-only ............................................................................... 26 4.3 interrupt enable register (ier) - read/write ....... .............. .............. ............ ........... ........... .......... . 26 4.3.1 ier versus receive fifo interrupt mode operation ......................................................................... ...... 26
xr16m752/xr68m752 ii high performance duart with 64-byte fifo rev. 1.1.1 4.3.2 ier versus receive/transmit fifo polled mode operation .................................................................. 27 4.4 interrupt status register (isr) - read-only ........... .............. .............. .............. .............. ............. .. 28 4.4.1 interrupt generation: .................................................................................................... .................................... 28 4.4.2 interrupt clearing: ...................................................................................................... ....................................... 28 t able 9: i nterrupt s ource and p riority l evel ....................................................................................................................... 29 4.5 fifo control register (fcr) - write-only................................................................................... ...... 29 t able 10: t ransmit and r eceive fifo t rigger l evel s election ............................................................................................ 30 4.6 line control register (lcr) - read/write................................................................................... ...... 31 t able 11: p arity selection .............................................................................................................................. .......................... 32 4.7 modem control register (m cr) or general purpose output s control - read/write.. 32 t able 12: r egister at a ddress o ffset 0 x 7 ............................................................................................................................. 33 t able 13: r egister at a ddress o ffset 0 x 6 ............................................................................................................................. 33 4.8 line status register (lsr) - read only..................................................................................... ......... 34 4.9 modem status register (msr) - read only .................................................................................... ... 34 4.10 scratch pad register (spr) - re ad/write ............. .............. .............. .............. .............. .............. .... 36 4.11 transmission control register (tcr) - read/write (requires efr bit-4 = 1)..................... 36 4.12 trigger level register (tlr) - read/write (requires efr bit-4 = 1) ...................................... 36 4.13 baud rate generator registers (dll, dlm and dld[3:0]) - read /write.............. ........... ....... 36 t able 14: s ampling r ate s elect .............................................................................................................................. ................. 36 4.14 enhanced feature register (efr) . ............ .............. .............. .............. .............. ........... ........... .......... 37 t able 15: s oftware f low c ontrol f unctions ........................................................................................................................ 37 4.14.1 software flow control registers (xof f1, xoff2, xon1, xon2) - read/write .............................. 38 t able 16: uart reset conditions for channel a and b ................................................................................ ............ 39 5.0 electrical characteristics ................................................................................................. ..... 40 a bsolute m aximum r atings ..................................................................................................................... 40 t ypical p ackage t hermal r esistance d ata (m argin of error : 15%) .............................................. 40 dc e lectrical c haracteristics ............................................................................................................. 40 ac e lectrical c haracteristics ............................................................................................................. 41 f igure 14. c lock t iming ............................................................................................................................... .............................. 42 f igure 15. m odem i nput /o utput t iming f or c hannels a & b ................................................................................................. 43 f igure 16. 16 m ode (i ntel ) d ata b us r ead t iming ................................................................................................................... 43 f igure 17. 16 m ode (i ntel ) d ata b us w rite t iming .................................................................................................................. 44 f igure 18. 68 m ode (m otorola ) d ata b us r ead t iming .......................................................................................................... 44 f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ......................................................... 45 f igure 19. 68 m ode (m otorola ) d ata b us w rite t iming ......................................................................................................... 45 f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ....................................................... 46 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b........................................ 46 f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b......................................... 47 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b............................ 47 f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b ............................ 48 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm )................................................................................... 49 p ackage d imensions (32 pin qfn - 5 x 5 x 0.9 mm )................................................................................ 50 p ackage d imensions (49 pin s hrink t hin b all g rid a rray - 4 x 4 mm ) ................................................. 51 r evision h istory ............................................................................................................................... ....... 52

▲Up To Search▲

Price & Availability of XR16M752IL32-F

	To Download XR16M752IL32-F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .